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| SSM4226M/GM DUAL N-CHANNEL ENHANCEMENT-MODE POWER MOSFET Low on-resistance Simple drive requirement High VGS rating D2 D1 D1 D2 BVDSS R DS(ON) G2 S2 30V 18m 8.2A ID SO-8 S1 G1 Description D1 D2 Advanced Power MOSFETs from Silicon Standard provide the designer with the best combination of fast switching, ruggedized device design, ultra low on-resistance and cost-effectiveness. G1 S1 G2 S2 This device is available with Pb-free lead finish (second-level interconnect) as SSM4226GM. Absolute Maximum Ratings Symbol VDS VGS ID @ TA=25C ID @ TA=70C IDM PD @ TA=25C TSTG TJ Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Continuous Drain Current Pulsed Drain Current 1 3 3 Rating 30 20 8.2 6.7 30 2 0.016 -55 to 150 -55 to 150 Units V V A A A W W/C C C Total Power Dissipation Linear Derating Factor Storage Temperature Range Operating Junction Temperature Range Thermal Data Symbol Rthj-a Parameter Thermal Resistance Junction-ambient 3 Value Max. 62.5 Unit C/W 8/06/2004 Rev.1.02 www.SiliconStandard.com 1 of 4 SSM4226M/GM Electrical Characteristics @ Tj=25oC (unless otherwise specified) Symbol BVDSS Parameter Drain-Source Breakdown Voltage Test Conditions VGS=0V, ID=250uA Min. 30 1 Typ. 0.03 15 20 5 12 12 8 31 12 320 230 Max. Units 18 28 3 1 25 100 30 V V/C m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF B VDSS/ Tj RDS(ON) Breakdown Voltage Temperature Coefficient Reference to 25C, ID=1mA Static Drain-Source On-Resistance 2 VGS=10V, ID=6A VGS=4.5V, ID=4A VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (Tj=25 C) Drain-Source Leakage Current (Tj=70 C) o o VDS=VGS, ID=250uA VDS=10V, ID=6A VDS=30V, VGS=0V VDS=24V ,VGS=0V VGS= 20V ID=8A VDS=24V VGS=4.5V VDS=15V ID=1A RG=3.3 ,VGS=10V RD=15 VGS=0V VDS=25V f=1.0MHz Gate-Source Leakage Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 2 1450 2320 Source-Drain Diode Symbol VSD Parameter Forward On Voltage 2 Test Conditions IS=1.7A, VGS=0V IS=8A, VGS=0V, dI/dt=100A/s Min. - Typ. 27 18 Max. Units 1.2 V ns nC trr Qrr Reverse Recovery Time Reverse Recovery Charge Notes: 1.Pulse width limited by Max. junction temperature. 2.Pulse width <300us , duty cycle <2%. 3.Surface mounted on 1 in2 copper pad of FR4 board ; 135C/Wwhen mounted on Min. copper pad. 8/06/2004 Rev.1.02 www.SiliconStandard.com 2 of 4 SSM4226M/GM 35 35 T A =25 o C 28 10V 5.0V 4.0V ID , Drain Current (A) 28 T A =150 o C 10V 5.0V 4.0V ID , Drain Current (A) 21 21 14 14 7 7 V G =3.0V V G =3.0V 0 0 1 1 2 2 3 0 0 1 1 2 2 3 V DS , Drain-to-Source Voltage (V) V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 80 1.8 I D =6.0A T A =25C 60 1.6 I D =6A V GS =10V Normalized RDS(ON) 2 4 6 8 10 12 1.4 RDS(ON) (m ) 40 1.2 1 20 0.8 0 0.6 -50 0 50 100 150 V GS , Gate-to-Source Voltage (V) T j , Junction Temperature ( o C) Fig 3. On-Resistance vs. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature 2.50 10 2.25 IS(A) 1 T j =150 o C T j =25 o C 0.1 0 0.4 0.8 1.2 1.6 VGS(th) (V) 2.00 1.75 1.50 1.25 1.00 -50 0 50 100 150 V SD ,Source-to-Drain Voltage (V) T j , Junction Temperature ( o C) Fig 5. Forward Characteristic of Fig 6. Gate Threshold Voltage Reverse Diode 8/06/2004 Rev.1.02 vs. Junction Temperature www.SiliconStandard.com 3 of 4 SSM4226M/GM 16 10000 f=1.0MHz I D =8A VGS , Gate to Source Voltage (V) 12 C (pF) V DS =15V V DS =20V V DS =24V Ciss 1000 8 Coss Crss 100 4 0 0 10 20 30 40 50 10 1 5 9 13 17 21 25 29 Q G , Total Gate Charge (nC) V DS , Drain-to-Source Voltage (V) Fig 7. Gate Charge Characteristics 100 1 Fig 8. Typical Capacitance Characteristics Duty factor=0.5 100us 10 Normalized Thermal Response (R thja) 0.2 1ms 0.1 0.1 0.05 ID (A) 1 10ms 100ms 1s 0.02 0.01 PDM 0.01 Single Pulse t T Duty factor = t/T Peak Tj = PDM x Rthja + Ta Rthja = 135/W 0.1 T c =25 o C Single Pulse 0.01 0.1 1 10 DC 0.001 100 0.0001 0.001 0.01 0.1 1 10 100 1000 V DS (V) t , Pulse Width (s) Fig 9. Maximum Safe Operating Area VDS 90% Fig 10. Effective Transient Thermal Impedance VG QG 4.5V QGS QGD 10% VGS td(on) tr td(off) tf Charge Q Fig 11. Switching Time Waveform Fig 12. Gate Charge Waveform Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 8/06/2004 Rev.1.02 www.SiliconStandard.com 4 of 4 |
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